1 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 the sy100ep14u is a high-speed, 2ghz differential pecl/ecl 1:5 fanout buffer optimized for ultra-low skew applications. within device skew is guaranteed to be less than 25ps over temperature and supply voltage. the wide supply voltage operation allows this fanout buffer to operate in 2.5v, 3.3v, and 5v systems. a v bb reference is included for single-supply or ac-coupled pecl/ecl input appli cat ions, t hu s elim inat ing resi st or net works. w hen interfacing to a single-ended or ac-coupled pecl/ecl input signal, connect the v bb pin to the unused /clk pin, and bypass the pin to v cc through a 0.01 f capacitor. the sy100ep14u features a 2:1 input mux, making it an ideal solution for redundant clock switchover applications. if only one input pair is used, the other pair may be left floating. in addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. enable or disable state is initiated only after the outputs are in a low state, thus eliminating the possibility of a ?runt? clock pulse. the sy100ep14u i/o are fully differential and 100k ecl compatible. differential 10k ecl logic can interface directly into the sy100ep14u inputs. the sy100ep14u is part of micrel?s high-speed clock synchronization family. for applications that require a diff er en t i/o com binat ion , c ons ul t t he mi crel web site at www. micrel. com, and choose f rom a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators. features description rev.: g amendment: /0 issue date: may 2010 ? guaranteed ac parameters over temp/voltage: ? > 2ghz f max ? < 25ps within-device skew ? < 275ps tr/tf time ? < 525ps prop delay ? 2:1 differential mux input ? flexible supply voltage: 2.5v/3.3v/5v ? wide operating temperature range: ?40 c to +85 c ? v bb reference for single-ended or ac-coupled pecl inputs ? 100k ecl compatible outputs ? inputs accept pecl/lvpecl/ecl/hstl logic ? 75k ? ? internal input pull-down resistors ? available in a 20-pin tssop package 2.5 v/ 3.3 v/5 v 1:5 l vpec l/pe cl/ ec l/h stl 2ghz c lock driver wit h 2:1 d iffe ren ti al input mux ecl pro? p rec is ion edge ? sy100ep14u ecl pro is a trademarks of micrel, inc. precision edge is a registered trademarks of micrel, inc.
2 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 package/ordering information ordering information (1) package operating package part n u m b e r t y p e range marking s y 100ep14uk4c k4-20-1 commercial xep14u s y 100ep14uk4ct r (2) k4-20-1 commercial xep14u s y 100ep14uk4i k4-20-1 i ndust rial xep 14u s y 100ep14uk4itr (2) k4-20-1 i ndust rial xep14u s y 100ep14uk4g (3) k4-20-1 indust rial xep14u wit h pb-f ree bar line indicat o r s y 100ep14uk4gtr (2, 3 ) k4-20-1 i ndust rial xep14u wit h pb-f ree bar line indicat o r notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs. 1 q0 /q0 q1 /q1 q2 /q2 q3 /q3 q4 /q4 20 vcc /en vcc / clk 1 clk 1 vbb / clk0 clk0 sel vee 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1 0 d q 20-pin tssop
3 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 pin description n o i t c n u f n i p clk0, /clk0 pecl, lvpecl, ecl, lvecl, hstl clock or data inputs. clk1, /clk1 internal 75k pull-down resistors on clk0, clk1, and internal 75k pull-up and 75k pull-down resistors or /clk0, /clk1. for single-ended applications, connect signal into clk0 and/or clk1 inputs. /clk0, /clk1 default condition is v cc /2 when left floating. clk0, clk1 default condition is low when left floating. q0 to q 4 lvpecl, pecl, ecl differential outputs : terminate with 50 to v cc ?2v. for single-ended applications, /q0 to /q 4 terminate the unused output with 50 to v cc ?2v /en lvpecl, pecl, ecl compatible synchronous enable : when /en goes high, the q out will go low and /q out will go high on the next low input clock transition. includes a 75k pull-down. default state is low when left floating. the internal latch is clocked on the falling edge of the input clock (clk0, clk1) sel lvpecl, pecl, ecl compatible 2:1 mux input signal select : when sel is low, clk0 input pair is selected. when sel is high, clk1 input pair is selected. includes a 75k pull-down. default state is low and clk0 is selected. v bb output reference voltage : equal to v cc ?1.7v (approx.), and used for single-ended input signals or ac-couple d applications. for single-ended pecl, lvpecl applications, bypass with a 0.01 f to v cc . for single-ended lvttl inputs, bypass to gnd. max. sink/source current is 0.5ma. v cc positive power supply : bypass with 0.1 f//0.01 f low esr capacitors. v ee negative power supply : lvpecl, pecl applications, connect to gnd. clk_sel active input 0 clk0, /clk0 1 clk1, /clk1 function table truth table (1) clk0 clk1 clk_sel /en q l x l l l h x l l h x l h l l x h h l h x x x h l * note 1. on next negative transition of clk0 or clk1.
4 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 t i n u e u l a v g n i t a r l o b m y s v cc ? v ee v 0 . 6 e g a t l o v y l p p u s r e w o p v in input voltage (v cc = 0v, v in not more negative than v ee ) ?6.0 to 0 v input voltage (v ee = 0v, v in not more positive than v cc ) +6.0 to 0 i out a m 0 5 s u o u n i t n o c ? t n e r r u c t u p t u o 0 0 1 e g r u s ? i bb v bb sink/source current (2) 0.5 ma t lead 0 6 2 + ) . c e s 0 2 , g n i r e d l o s ( e r u t a r e p m e t d a e l c t a 5 8 + o t 0 4 ? e g n a r e r u t a r e p m e t g n i t a r e p o c t store 0 5 1 + o t 5 6 ? e g n a r e r u t a r e p m e t e g a r o t s c v k 5 . 1 > s n i p l l a , l e d o m y d o b n a m u h 3 8 8 . d t s l i m d s e ja package thermal resistanc e ?still-air (single-layer pcb ) 115 (junction-to-ambient ) ?still-air (multi-layer pcb) 75 c/w ?500lfpm (multi-layer pcb) 65 jc 1 2 e c n a t s i s e r l a m r e h t e g a k c a p c/w (junction-to-case) note 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operati on is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ra tlng conditions for extended periods may affect device reliability. note 2. due to the limited drive capability, use for inputs of same package only. absolute maximum ratings (1) t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit condition v c c power supply voltage v (pecl) 4.5 5.0 5.5 4.5 5.0 5.5 4.5 5.0 5.5 (lvpecl) 2.37 3.3 3.8 2.37 3.3 3.8 2.37 3.3 3.8 (ecl) ?4.5 ?5.0 ?5.5 ?4.5 ?5.0 ?5.5 ?4.5 ?5.0 ?5.5 (lvecl) ?3.8 ?3.3 ?2.37 ?3.8 ?3.3 ?2.37 ?3.8 ?3.3 ?2.37 i c c power supply curren t ? ? 75 ? 6 8 7 8 ? ? 8 2 ma i ih input high curren t ? ? 150 ? ? 150 ? ? 150 a v i n = v i h i i l input low curren t d 0.5 ? ? 0.5 ? ? 0.5 ? ? a v i n = v i l /d ?150 ? ? ?150 ? ? ?150 ? ? a v i n = v i l c in input capacitanc e (tssop) ???? 0.75 ???? pf note 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establis hed. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. dc electrical characteristics (1)
5 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage (2) 555?875 555?875 555?875 mv (single-ended) v ih input high voltage (2) 1335 ? 1620 1335 ? 1620 1335 ? 1620 mv (single-ended) v ol output low voltage 555 680 805 555 680 805 555 680 805 mv 5 0 t o v c c ?2v v oh output high voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 5 0 t o v c c ?2v v ihcmr input high voltage 1.2 ? v c c 1.2 ? v c c 1.2 ? v c c v common mode range (3) note 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establis hed. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. inpu t and output varies 1:1 with v cc . note 2. v bb reference is not functional for v cc < 3.0v. external v bb equivalent is required. note 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differen- tial input signal. (100kep) lvpecl dc electrical characteristics (1) v cc = 2.5v 5%, v ee = 0v t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1355 ? 1675 1355 ? 1675 1355 ? 1675 mv (single-ended) v ih input high voltage 2075 ? 2420 2075 ? 2420 2075 ? 2420 mv (single-ended) v ol output low voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 5 0 t o v c c ?2v v oh output high voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv 5 0 t o v c c ?2v v bb reference voltage (2) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v c c = 3.3v v ihcmr input high voltage 1.2 ? v c c 1.2 ? v c c 1.2 ? v c c v common mode range (3) note 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establis hed. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. inpu t and output varies 1:1 with v cc . note 2. single-ended input operation is limited v cc 3.0v in lvpecl mode. v bb reference varies 1:1 with v cc . note 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differen- tial input signal. (100kep) lvpecl dc electrical characteristics (1) v cc = 3.3v 10%; v ee = 0v
6 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 3055 ? 3375 3055 ? 3375 3055 ? 3375 mv (single-ended) v ih input high voltage 3775 ? 4120 3775 ? 4120 3775 ? 4120 mv (single-ended) v ol output low voltage 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv 5 0 t o v c c ?2v v oh output high voltage 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv 5 0 t o v c c ?2v v bb output voltage reference (2) 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v c c = +5.0v v ihcmr input high voltage (3) 2.0 ? v cc 2.0 ? v cc 2.0 ? v cc v common mode range (100kep) pecl dc electrical characteristics (1) v cc = 5.0v 10%, v ee = 0v note 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establis hed. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. inpu t and output parameters are at v cc = 5.0v. they vary 1:1 with v cc . note 2. v bb reference varies 1:1 with v cc . note 3. the v ihcmr range is referenced to the most positive side of the differential input signal. single-ended input clk pin operation is limite d to v cc 3.0v in pecl mode. t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage ?194 5 ? ?162 5 ?1945 ? ?1625 ?1945 ? ?1625 mv (single-ended) v ih input high voltage ?116 5 ? ?880 ?1165 ? ?880 ?1165 ? ?880 mv (single-ended) v ol output low voltage ?194 5 ?182 0 ?169 5 ?1945 ?1820 ?1695 ?1945 ?1820 ?1695 mv 5 0 t o v c c ?2v v oh output high voltage ?114 5 ?102 0 ?089 5 ?1145 ?1020 ?0895 ?1145 ?1020 ?0895 mv 5 0 t o v c c ?2v v bb output reference voltage (2) ?152 5 ?142 5 ?132 5 ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 mv v ihcmr input high voltage v common mode range (3) v e e +1.2 0.0 v e e +1.2 0.0 v e e +1.2 0.0 (100kep) lvecl dc electrical characteristics (1) v ee = ?2.37v to ?3.8v; v cc = 0v note 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establis hed. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. inpu t and output parameters vary 1:1 with v cc . note 2. single-ended input operation is limited v ee ?3.0v in ecl/lvecl mode. v bb reference varies 1:1 with v cc . note 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal.
7 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 (100k) ecl/lvecl dc electrical characteristics (1) v cc = 0v, v ee = ?5.5v to ?3.0v t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage ?194 5 ? ?162 5 ?1945 ? ?1625 ?1945 ? ?1625 mv v ih input high voltage ?122 5 ? ?880 ?1225 ? ?880 ?1225 ? ?880 mv v ol output low voltage (2) ?194 5 ?182 0 ?169 5 ?1945 ?1820 ?1695 ?1945 ?1820 ?1695 mv 5 0 t o v c c ?2v v oh output high voltage (2) ?114 5 ?102 0 ?895 ?1145 ?1020 ?895 ?1145 ?1020 ?895 mv 5 0 t o v c c ?2v v bb output reference voltage (3) ?152 5 ?142 5 ?132 5 ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 mv v ihcmr input high voltage v e e +1.2 0.0 v e e +1.2 0.0 v e e +1.2 0.0 v common mode range (4) note 1. 10ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and ou tput parameters vary 1:1 with v cc . note 2. all loading with 50 to v cc ?2.0v. note 3. single-ended input operation is limited v ee ?3.0v in ecl/lvecl mode. v bb reference varies 1:1 with v cc . note 4. v ihcmr (min) varies 1:1 with v ee , (max) varies 1:1 with v cc . the v ihcmr is referenced to the most positive side of the differential input signal. t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit v ih input high voltage 1200 ? ? 1200 ? ? 1200 ? ? mv v il input low voltage ? ? 400 ? ? 400 ? ? 400 mv v x input crossover voltag e 680?900 680?900 680?900 mv hstl input dc electrical characteristics v cc = 2.37v to 3.8v; v ee = 0v
8 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 t a = ?40 c t a = +25 c t a = +85 c symbol paramete r min. typ. max. min. typ. max. min. typ. max. unit f max m a x i m u m frequenc y (1) 2 ? ?2? ? 2 ? ? ghz t plh p ecl/ecl ( v c c = 5v) t phl propagat ion delay to ou t put s p 0 0 6 0 3 3 0 5 2 0 5 4 0 3 3 0 5 2 0 0 4 0 3 3 0 5 2 ) l a i t n e r e f f i d ( n i in (single-ended) ???? 355 ??? ? ps lvp ecl/ l v ecl ( v c c = 2 . 37v t o 3 . 8 v ) p ropagat ion delay to ou t put s p 5 2 5 0 5 3 5 7 2 5 7 4 0 5 3 5 7 2 5 2 4 0 5 3 5 7 2 ) l a i t n e r e f f i d ( n i in (single-ended) ???? 375 ??? ? ps t skew (2) p ecl/ecl ( v c c = 5v) within-device skew (diff. ) ? 2 5 3 5 ? 30 45 ? 4 0 5 0 ps part-to-part skew (diff.) ? 100 125?150 175?175 200 ps lvp ecl/ l v ecl ( v c c = 2 . 37v t o 3 . 8v) within-device skew (diff. ) ? 1 0 2 5 ? 15 25 ? 1 5 2 5 ps part-to-part skew (diff.) ? 100 125?150 175?200 225 ps t s set-up time (3) /en to clk 100 50 ? 100 50 ? 100 50 ? ps t h hold time (3) /en to clk 200 140?200 140?200 140 ? ps v pp minimum input swing 150 800 1200 150 800 1200 150 800 1200 mv t r , t f p ecl/ecl ou t put ris e /fall times s p 0 0 3 5 2 2 0 1 1 0 7 2 0 8 1 5 0 1 0 4 2 0 8 1 0 0 1 ) % 0 8 o t % 0 2 ( lvpecl/lvecl ( v c c = 2 . 37v t o 3 . 8v) 9 0 130 225 9 5 130 250 100 150 275 p s note 1. f max is defined as the maximum toggle frequency. measured with 750mv input signal, 50% duty cycle, all loading with 50w to v cc ?2v. note 2. skew is measured between outputs under identical transitions. note 3. set-up and hold times apply to synchronous applications that intend to enable/disable before then ext clock cycle. for asynchro nous applica- tions, set-up and hold time does not apply. ac electrical characteristics lvpecl: v cc = 2.37v to 2.625v, v ee = 0v; pecl: v cc = 4.50v to 5.50v, v ee = 0v; ecl: v ee = ?4.50v to ?5.5v, v cc = 0v; lvecl: v ee = ?2.37v to ?3.8v, v cc = 0v
9 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 termination recommendations r2 82 r2 82 z o = 50 z o = 50 +3.3v +3.3v v t = v cc ?2v r1 130 r1 130 +3.3v figure 1. parallel termination?thevenin equivalent note 1. for +2.5v systems: r1 = 250 , r2 = 62.5 note 2. for +5.0v systems: r1 = 82 , r2 = 130 z = 50 z = 50 50 50 50 v 3 . 3 + v 3 . 3 + ? n o i t a n i t s e d ? ? e c r u o s ? r b figure 2. three-resistor ?y?termination? note 1. power-saving alternative to thevenin termination. note 2. place termination resistors as close to destination inputs as possible. note 3. r b resistor sets the dc bias voltage, equal to v t . for +3.3v systems r b = 46 to 50 . for +5v systems, r b = 110 . +3.3v +3.3v 50 z o = 50 0.01 f v bb r2 82 +3.3v +3.3v r1 130 r1 130 r2 82 v t = v cc ?2v q /q +3.3v figure 3. terminating unused i/o note 1. unused output (/q) must be terminated to balance the output. note 2. micrel's differential i/o logic devices include a v bb reference pin . note 3. connect unused input through 50 to v bb . bypass with a 0.01 f capacitor to v cc , not gnd. note 4. for +2.5v systems: r1 = 250 , r2 = 62.5 .
10 precision edge ? sy100ep14u micrel, inc. m9999-060910 hbwhelp@micrel.com or (408) 955-1690 20-pin tssop (k4-20-1) .10 .004 + .10 ? .00 + .004 ? .000 .05 0 . 002 + .10 ? .00 + .004 ? .000 .10 .004 r e v . 0 1 micrel, inc. 2180 fortune drive san jose, ca 9513 1 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is as sumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated. package notes: note 1. package meets level 1 moisture sensitivity.
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